BERT Bit Error Location Analyzer

  BitWise Laboratories Bit Error Location Analyzer measures BER and error location statistics for up to two synchronous NRZ data streams at data rates from 1.0 – 28.0 Gbits/sec. Flexible timing and threshold controls, auto pattern detection, simple quasi-eye diagrams.

Key Features

  • 1.0 – 28.0 Gbps
  • 2 synchronous NRZ data channel inputs
  • 1 shared clock input
  • Trigger outputs
  • Independent channel delay and threshold
  • PRBS or user-specified pattern synchronization
  • Independent channel or bit-interleaved synchronization
  • BER and Error Location Analysis
  • Compact Design

   The Bit Error Location Analyzer measures BER and error location statistics in 2 synchronous NRZ data streams at data rates 1.0 – 28.0 Gbps each.  Signal interfacing utilizes flexible timing and threshold controls, auto pattern detection, a large number of true and inverted PRBS patterns, user-defined patterns, and simple quasi-eye diagrams.  2-Channel processing can be unlinked, linked, or bit-interleaved, and channel-to-channel synchronization can be determined automatically using a 64-bit barrel shifting function.

   Provides BER measurements and Strip chart.  Also provides many Error Location analyzers such as Burst Length Histogram, Error Free Interval Histogram, Modulo-N Histogram, Modulo Pattern-Length Histogram, and others.  Forward Error Correction (FEC) system emulation features simulate a configurable Forward Error Correction (FEC) system and calculates the correction strength (T) required to fully correct the raw errors.  Data pattern analysis allows you to measure run lengths and wander within a user-selectable window interval.

   The user interface is served as a website from the device and is accessible from any desktop or mobile web browser.  The device does not require connection to the Internet.  Automation control is provided via TCP/IP socket interface using ASCII commands.  Analysis results can be captured and downloaded in CSV format.  

Bit Error Location Analyzer

Bit Error Location Analyzer Specification Value Notes
Input Clock 0.5 – 14.0 GHz, 2.92 mm, Single-ended, AC coupled Selectable full-rate or 1/2-rate DDR clock
Input Data 1.0 – 28.0 Gbps, 2.92 mm, Differential, AC coupled 2 channels clocked by the same clock with independent delays
Threshold -1.0 to 1.0 V V-Low to V-High
Variable Delay Range 0 – 140 ps Each independent channel
Variable Delay Resolution 0.1 ps
BER Measurements Bits, Errors, Instantaneous BER, Total BER, Strip Chart Individual and combined channel measurements
Error Location Analysis Symbol Error Rate, Block Histogram, Burst Length Histogram, Correlation Histogram, Pattern-sensitivity Histogram, Error Free Interval Histogram, T-value Strip Chart Individual and combined channel measurements
PRBS Patterns PRBSn, n=7,11,13,15,20,23,31 True or inverted
User Patterns 8,192 128-bit words, 2.0 Megabits, each channel Selectable Grab-n-Go or Shift-n-Sync synchronization
Output Triggers SMA, pattern sync, pulse-stretched error flag
Power Supply 100-240 VAC to 12V at 5A CE, FCC, UL Certified
Power 22 watts
Dimensions 6″ (L) x 7-1/2″ (W) x 2-1/2″ (H)

Bit Error Location Analyzer Online Help

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