Pattern Generator

BERT Pattern Generator

The Pattern Generator creates clock and data patterns used as stimulus for developing and evaluating digital communications systems and components. The Pattern Generators offers flexibility to create data streams of varying PRBS or user-defined patterns, with selectable data rate, signal offset, amplitude, timing and preemphasis to help you create the test signals you need.

BERT Pattern Generator

Key Features

Compact 2-Channel Design
1.0 – 28.0 Gbps per Channel
PRBS and User Patterns
Internal Clock Synthesizer
External Clock Input
2 Synchronous Data Output Channels
4 Tap Preemphasis
Single-ended or Differential

AC or DC coupled Data Outputs
Optional Jitter Insertion (DDR5SA)
Programmable signal levels

Description

The Pattern Generator creates data patterns used as stimulus for developing and evaluating digital communications systems and components. The Pattern Generators offers flexibility to create data streams of varying PRBS or user-defined patterns, with selectable data rate,, timing and pre-emphasis to help you create the test signals you need.

The Pattern Generator is a compact instrument that uses a built-in synthesizer or accepts an external clock input that is used to generate two channels of NRZ data at rates from 1 to 28 Gbps. Variable output delay is available on each channel for precise phase alignment. Each channel is DC-coupled and supports 4 Tap pre-emphasis with differential amplitude up to 2 Vpp. Channel pattern sequence output can be synchronized to combine properly to form a higher speed 2:1 multiplex.

External triggers can be used to trigger your oscilloscope on clock- or pattern-based triggers. A built-in error injector with selectable error profiles enables creating single-shot and repeating error signatures.

A built-in calibration input provides sub-rate error detection that allows you to examine eye-diagrams and BER Bathtub analysis for sub-rate return channels. This is perfect for use with applications that utilize a sub-rate loopback for receiver testing, such as DDR5.

Diagram

Specifications

Pattern Generator Specification	Value	Notes
Internal Synthesizer	0.5 – 14.0 GHz	1/2-rate DDR clock
Data Rate	1.0 – 28.0 Gbps	2 synchronous channels
Amplitude	250 mV – 2.0 V	Differential
Offset	-2.0 to 3.0 V	V-Mid
Variable Delay Range	0 – 150 ps	Each independent channel
Variable Delay Resolution	0.1 ps
Rise/Fall Time	15 ps	20/80, typical
Jitter	Clock 350 fs RMS, Data 600 fs RMS	typical
Preemphasis	4 Tap for each channel	Tap-2 is always 1.0
PRBS Patterns	PRBSn, n=7,11,13,15,20,23,31	True or inverted
User Patterns	2.0 Megabits each channel	Organized as 8,192 128-bit words, with looping
Output Data	2.92 mm, 50 Ohms, AC or DC Selectable	2 channels with independent delays
Output Clock	SMA, 50 Ohm, AC coupled,, DIfferential
Output Triggers	SMA, clock or data pattern related triggers
Power Supply	100-240 VAC to 12V at 5A	CE, FCC, UL Certified
Power	70 watts
Dimensions	6″ (L) x 7-1/2″ (W) x 2-1/2″ (H)

Media