The Bit Error Location Analyzer measures BER and error location statistics in 2 synchronous NRZ data streams at data rates 1.0 – 28.0 Gbps each. Signal interfacing utilizes flexible timing and threshold controls, auto pattern detection, a large number of true and inverted PRBS patterns, user-defined patterns, and simple quasi-eye diagrams. 2-Channel processing can be unlinked, linked, or bit-interleaved, and channel-to-channel synchronization can be determined automatically using a 64-bit barrel shifting function.
Provides BER measurements and Strip chart. Also provides many Error Location analyzers such as Burst Length Histogram, Error Free Interval Histogram, Modulo-N Histogram, Modulo Pattern-Length Histogram, and others. Forward Error Correction (FEC) system emulation features simulate a configurable Forward Error Correction (FEC) system and calculates the correction strength (T) required to fully correct the raw errors. Data pattern analysis allows you to measure run lengths and wander within a user-selectable window interval.
The user interface is served as a website from the device and is accessible from any desktop or mobile web browser. The device does not require connection to the Internet. Automation control is provided via TCP/IP socket interface using ASCII commands. Analysis results can be captured and downloaded in CSV format.